Many emerging memory devices use an application of three dimensional device stacking, where the memory cells are created on the semiconductor substrate in three dimensions instead of only two dimensions in a plane. The memory structure typically includes a metal layer above the memory array to provide the connecting lines for the circuit, such as bitline connections or wordline connections. The structures often employ vias that reach down to circuit features associated with driving the memory array. Typically the vias are formed with chemical vapor deposition (CVD) to form metal in a vertical structure.
Reducing the number of processing steps typically improves cost and process flow. However, reducing the number of processing steps can require tradeoffs between the benefits and unintended effects of certain architectural choices. For example, the inclusion of tungsten silicon nitride in the circuit can provide reset current (Ireset) improvement for certain memory cells, but the resistivity of the tungsten silicon nitride increases losses to current flow in the via.
Descriptions of certain details and implementations follow, including non-limiting descriptions of the figures, which may depict some or all examples, and well as other potential implementations.